Lateral high-voltage MOS transistors having an n-conductive channel are typically formed on p-conductive wafers in the form of a DMOS transistor, in which a topology of the doped zones corresponds to a “double-diffused” MOS, in short DMOS transistor, wherein a drain region is of the same conductivity type as a well doping, i.e., of an n-type conductivity. Lateral high-voltage transistors having a p-conductive channel, i.e., high-voltage MOS transistors being complementary to the former transistor, are fabricated on p-conductive wafers typically in the form of a drain extension transistor, in which drain and drift regions are of inverse conductivity type compared to the n-well that is also provided in this case. In the context of the present application the term lateral high-voltage MOS transistor describes both of these transistor types.
In lateral DMOS (LDMOS) transistors for applications using high electric voltages it is known from U.S. 2003/0193067 A1 (FIG. 2) to use a so-called double RESURF structure. RESURF is the abbreviation of the term reduced surface field.
A double RESURF structure comprises a doped region above and below a drift region or a drain extension region of an LDMOS transistor that has the inverse conductivity type compared to a drift region and a drain extension region, respectively. If, for example, the drift region is n-conductive, then the substrate region positioned below and the doped region incorporated in the drift zone are p-conductive. The doped regions typically have a dopant concentration in the same order of magnitude as the drift region, however, in the vertical direction an integrated total doping of at most about 1*1012 cm−2.
Upon applying a voltage to the drain electrode of the lateral high-voltage transistor by means of the double RESURF structure a depletion zone is generated, which extends along the boundary between the drift region and a substrate region positioned below of inverse conductivity type. A further depletion zone forms between the drift region itself and the doped region incorporated below the surface of the drift region.
In this manner a full depletion of the drift region with respect to charge carriers is caused by these two reverse-biased pn junctions, thereby resulting in a desired increase of the breakthrough voltage of the lateral high-voltage MOS transistor. At the same time the concentration of charge carriers in the drift region can be increased by incorporating the doped region into the drift region, thereby reducing the on-resistance of the lateral high-voltage MOS transistor. This is because the magnitude of the breakthrough voltage in reversed bias mode is solely determined by the integrated net doping of the drift region and of the doped regions incorporated therein. For this purpose, however, the incorporated doped region compensates the dopant concentration of the drift region. Hence, relatively high dopant concentrations may be used in the drift region, thereby resulting in an increase of its conductivity and thus reducing Ron without reducing the breakthrough voltage. The method can appropriately be extended to the incorporation of a plurality of stacked p-zones into the drift zone, which are separated from each other, and this is then referred to as a multi RESURF structure or as a superjunction structure.
The production of such multiple RESURF structures together with other components, in particular with complementary high-voltage MOS transistors, is, however, complex and requires additional masking steps for incorporating the doped regions into the drift region compared to simple lateral high-voltage MOS transistors.
The technical object underlying the present invention is to provide a method for fabricating a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to the former one, with which a double or multiple RESURF structure can be formed with reduced effort.